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1 isl28233, isl28433 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. dual and quad micropower, zero-drift, rrio operational amplifiers isl28233, isl28433 the isl28233 and isl28433 are dual and quad micropower, zero-drift operational amplifiers that are optimized for single and dual supply operation from 1.65v to 5.5v and 0.825v to 2.75v. their low supply current of 18a and wide input range enable the isl28233, isl28433 to be an excellent general purpose op amp for a range of applications. the isl28233 and isl28433 are ideal for handheld devices that operate off 2 aa or single li-ion batteries. the isl28233 is available in an 8 ld msop package. the isl28433 is available in 14 ld tssop and 14 ld soic packages. all devices operate over the temperature range of -40c to +85c. features ? low input offset voltage . . . . . . . . . . . 8v, max. ? low offset drift . . . . . . . . . . . . . 0.06v/c, max ? quiescent current (per amplifier) . . . . . 18a, typ. ? single supply range . . . . . . . . . +1.65v to +5.5v ? dual supply range . . . . . . . . 0.825v to 2.75v ? low noise (0.01hz to 10hz) . . . . . . . 1.1v p-p , typ. ? rail-to-rail inputs and output ? input bias current . . . . . . . . . . . . . 110pa, max. ? operating temperature range . . . -40c to +85c applications ? bi-directional current sense ? temperature measurement ?medical equipment ? electronic weigh scales ? precision/strain gauge sensor ? precision regulation ? low ohmic current sense ?high gain analog front ends typical application v os vs temp bi-directional current sense amplifier i-sense+ 0.1 4.99k 4.99k 499k 499k + - v+ v- gnd v sense out v ref v + +1.65v to +5.5v i-sense- -8 -6 -4 -2 0 2 4 6 8 -40 -20 0 20 40 60 80 100 temperature (c) input offset voltage (v) max median min n = 60 march 25, 2010 fn6942.0
2 fn6942.0 march 25, 2010 ordering information part number (note 3) part marking package (pb-free) pkg. dwg. # isl28233iuz (note 2) 8233z 8 ld msop m8.118a isl28233iuz-t7 (notes 1, 2) 8233z 8 ld msop m8.118a coming soon isl28433ibz (note 2) 28433 ibz 14 ld soic mdp0027 coming soon isl28433ibz-t7 (notes 1, 2) 28433 ibz 14 ld soic mdp0027 coming soon ISL28433IVZ (note 2) 28433 ivz 14 ld tssop mdp0044 coming soon ISL28433IVZ-t13 (notes 1, 2) 28433 ivz 14 ld tssop mdp0044 coming soon isl28433irtz (note 2) tbd 14 ld 3x4 mm tdfn tbd coming soon isl28433irtz-t13 (notes 1, 2) tbd 14 ld 3x4 mm tdfn tbd notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pa ckaged products employ special pb-free material sets, molding compound s/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free produc ts are msl classified at pb-free peak refl ow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for isl28233, isl28433 . for more information on msl please see techbrief tb363 . pin configurations isl28233 (8 ld msop) top view isl28433 (14 ld soic) top view isl28433 (14 ld tdfn) top view 1 2 3 4 8 7 6 5 out_a in-_a in+_a v+ out_b in-_b v- in+_b + - +- out_a in-_a in+_a v + in+_b in-_b out_b out_d in-_d in+_d v - in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +- out_a in-_a in+_a v + in+_b in-_b out_b out_d in-_d in+_d v - in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +- isl28233, isl28433
3 fn6942.0 march 25, 2010 isl28433 (14 ld tssop) top view pin configurations (continued) out_a in-_a in+_a v + in+_b in-_b out_b out_d in-_d in+_d v - in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +- pin descriptions isl28233 (8 ld msop) isl28433 (14 ld tssop, soic, tdfn) pin name function equivalent circuit 3 3 in+_a non-inverting input circuit 1 55in+_b 10 in+_c 12 in+_d 4 11 v- negative supply 2 2 in-_a inverting input (see circuit 1) 66in-_b 9in-_c 13 in-_d 1 1 out_a output circuit 2 77out_b 8out_c 14 out_d 8 4 v+ positive supply pd nc thermal pad thermal pad. connect to most negative supply. tdfn package only. in- v+ in+ v- + - + - clock gen + drivers v + v- out isl28233, isl28433
4 fn6942.0 march 25, 2010 absolute maximum ratings thermal information max supply voltage v+ to v- . . . . . . . . . . . . . . . . . . . .6.5v max voltage vin to gnd . . . . . . (v- - 0.3v) to (v+ + 0.3v)v max input differential voltage . . . . . . . . . . . . . . . . . . 6.5v max input current . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma max voltage vout to gnd (10s) . . . . . . . . . . . . . . . .3.0v esd tolerance human body model . . . . . . . . . . . . . . . . . . . . . . . 4000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 400v charged device model . . . . . . . . . . . . . . . . . . . . . 2000v latch-up passed per jesd78b . . . . . . . . . . . . . . . . +125c thermal resistance (typical) ja (c/w) jc (c/w) 14 ld tssop (notes 4, 6) . . . . . . . 110 tbd 14 ld soic (notes 4, 6) . . . . . . . . 75 tbd 14 ld tdfn (notes 4, 5) . . . . . . . . tbd tbd 8 ld msop (notes 4, 6) . . . . . . . . 180 65 maximum storage temperature range . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. for jc , the ?case temp? location is taken at the package top center. electrical specifications v + = 5v, v - = 0v, vcm = 2.5v, t a = +25c, r l = 10k , unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter description conditions min (note 7) typ max (note 7) unit dc specifications v os input offset voltage -8 2 8 v -11.9 - 11.9 v tcv os input offset voltage temperature coefficient -0.06 0.02 0.06 v/c i os input offset current - 1 - pa tci os input offset current temperature coefficient -0.11- pa/c i b input bias current -110 30 110 pa -110 - 110 pa tci b input bias current temperature coefficient -0.49- pa/c common mode input voltage range v+ = 5.0v, v- = gnd -0.1 - 5.1 v cmrr common mode rejection rati o vcm = -0.1v to 5.1v 118 125 - db 115 -db psrr power supply rejection ratio vs = 1.65v to 5.5v 110 138 - db 110 -db v oh output voltage swing, high r l = 10k 4.965 4.981 - v v ol output voltage swing, low 18 35 mv a ol open loop gain r l = 1m 174 - db v + supply voltage guaranteed by psrr 1.65 - 5.5 v i s supply current, per amplifier r l = open - 18 25 a -- 35 a isl28233, isl28433
5 fn6942.0 march 25, 2010 i sc+ output source short circuit current r l = short to ground or v+ 13 17 26 ma i sc- output sink short circuit current -26 -19 -13 ma ac specifications gbwp gain bandwidth product f = 50khz a v = 100, r f = 100k , r g =1k , r l = 10k to v cm -400- khz e n v p-p peak-to-peak input noise voltage f = 0.01hz to 10hz - 1.1 - v p-p e n input noise voltage density f = 1khz - 65 - nv/ (hz ) i n input noise current density f = 1khz - 72 - fa/ (hz) f = 10hz - 79 - fa/ (hz) c in differential input capacitance f = 1mhz - 1.6 - pf common mode input capacitance - 1.12 - pf transient response sr positive slew rate v out = 1v to 4v, r l = 10k -0.2- v/s negative slew rate - 0.1 - v/s t r , t f , small signal rise time, t r 10% to 90% a v = +1, v out = 0.1v p-p , r f = 0 , r l = 10k , c l =1.2pf -1.1- s fall time, t f 10% to 90% - 1.1 - s t r , t f large signal rise time, t r 10% to 90% a v = +1, v out = 2v p-p , r f =0 , r l = 10k , c l =1.2pf -8- s fall time, t f 10% to 90% - 10 - s t s settling time to 0.1%, 2v p-p step a v = +1, r f = 0 , r l =10k , c l = 1.2pf -35- s t recover output overload recovery time, recovery to 90% of output saturation a v = +2, r f = 10k , r l =open , c l = 3.7pf - 10.5 - s note: 7. parameters with min and/or max limits are 100% tested at +2 5c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v + = 5v, v - = 0v, vcm = 2.5v, t a = +25c, r l = 10k , unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description conditions min (note 7) typ max (note 7) unit isl28233, isl28433
6 fn6942.0 march 25, 2010 n typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. figure 1. input offset voltage vs supply voltage figure 2. v os vs temperature figure 3. v os vs temperature figure 4. median i b+ vs temperature figure 5. median i b- vs temperature figure 6. median i os vs supply voltage vs temperature -4 -3 -2 -1 0 1 2 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) input offset voltage (v) max median min n = 59 -8 -6 -4 -2 0 2 4 6 8 -40-20 0 20406080100 temperature (c) input offset voltage (v) max median min n = 59 v s = 1v v in = 0v r l =open -8 -6 -4 -2 0 2 4 6 8 -40-20 0 20406080100 temperature (c) input offset voltage (v) n = 60 v s = 2.5v v in = 0v r l =open max median min -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 temperature (c) input bias current (pa) n = 54 v s = 1.65v v s = 5v -20 -10 0 10 20 30 40 50 60 70 80 -40-20 0 20406080100 temperature (c) input bias current (pa) n = 54 v s = 1.65v v s = 5v -40 -30 -20 -10 0 10 20 -40-20 0 20406080100 n = 54 temperature (c) input offset current (pa) v s = 1.65v v s = 5v isl28233, isl28433
7 fn6942.0 march 25, 2010 figure 7. median supply current vs temperature vs supply voltage figure 8. supply current vs temperature figure 9. supply current vs temperature figure 10. input noise voltage 0.1hz to 10hz figure 11. input noise voltage density vs frequency figure 12. input noise current density vs frequency typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) 0 5 10 15 20 25 30 -40-20 0 20406080100 n = 30 temperature (c) supply current (a) v s = 1.65v v s = 5v 12 14 16 18 20 22 24 26 28 -40 -20 0 20 40 60 80 100 n = 30 temperature (c) supply current (a) max median min v s = 0.825v v in = 0v r l =open 12 14 16 18 20 22 24 26 28 -40 -20 0 20 40 60 80 100 temperature (c) supply current (a) v s = 2.5v v in = 0v r l =open n = 30 max median min -1000 -800 -600 -400 -200 0 200 400 600 800 1000 0 50 100 150 200 250 300 350 400 450 500 frequency (hz) normalized gain (db) v s = 5v rl = 100k rg = 10, rf = 100k av = 10,000 cl = 3.7pf frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 0.001 0.01 0.1 1 10 100 1k 10k 100k v s = 5v av = 1 frequency (hz) 0.01 0.1 1.0 0.001 0.01 0.1 1 10 100 1k 10k 100k input noise current (pa/ hz) v s = 5v av = 1 isl28233, isl28433
8 fn6942.0 march 25, 2010 figure 13. frequency response vs open loop gain, r l = 10k figure 14. frequency response vs open loop gain, r l = 10m figure 15. gain vs frequency vs r l , v s = 0.8v figure 16. gain vs frequency vs r l , v s = 2.5v figure 17. gain vs frequency vs feedback resistor values r f /r g figure 18. gain vs frequency vs v out, r l = open typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -100 -50 0 50 100 150 200 1 100 10k 100k 1m 10m open loop gain (db)/phase () frequency (hz) rl = 10k simulation cl = 100pf gain phase 1k 10 100m 10m 1m 0.1m -100 -50 0 50 100 150 200 open loop gain (db)/phase () frequency (hz) rl = 10m simulation cl = 100pf gain phase 1 100 10k 100k 1m 10 m 1k 10 100m 10m 1m 0.1m -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m frequency (hz) normalized gain (db) rl = 10k rl = 49.9k rl = open rl = 1k rl = 100k v s = 0.8v a v = +1 v out = 10mv p-p c l = 3.7pf frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 rl = 100k rl = open rl = 1k v s = 2.5v a v = +1 v out = 10mv p-p c l = 3.7pf rl = 49.9k rl = 10k 1 2 3 4 5 6 7 8 9 10 frequency (hz) gain (db) 100 1k 10k 100k 1m 10m 0 v s = 2.5v r l = 100k a v = +2 v out = 10mv p-p c l = 3.7pf rf = rg = 100k rf = rg = 10k rf = rg = 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m v out = 100mv v out = 1v v out = 500mv v out = 250mv v out = 10mv v s = 2.5v r l = open a v = 1 c l = 3.7pf isl28233, isl28433
9 fn6942.0 march 25, 2010 figure 19. frequency resp onse vs closed loop gain figure 20. gain vs frequency vs supply voltage figure 21. gain vs frequency vs c l figure 22. cmrr vs frequency, v s = 2.5v figure 23. psrr vs frequency, v s = 2.5v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) av = 1 av = 10 av = 100 av = 1000 v+ = 5v v out = 10mv p-p c l = 3.7pf r l = 100k rg = 10k, rf = 100k rg = 100, rf = 100k rg = 1k, rf = 100k rg = open, rf = 0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m r l = 100k a v = +1 v out = 10mv p-p c l = 3.7pf v s = 0.8v v s = 1.5v v s = 0.7v v s = 2.75v -10 -8 -6 -4 -2 0 2 4 6 8 frequency (hz) normalized gain (db) 100 1k 10k 100k 1m 10m cl = 824pf cl = 224pf cl = 474pf cl = 51pf cl = 3.7pf cl = 104pf v s = 2.5v r l = 100k a v = +1 v out = 10mv p-p -140 -120 -100 -80 -60 -40 -20 0 20 frequency (hz) cmrr (db) 100 1k 10k 100k 1m 10m v s = 2.5v r l = 100k a v = +1 v cm = 1v p-p simulation -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (hz) psrr (db) 100 1k 10k 100k 1m 10m psrr- psrr+ v s = 2.5v r l = 100k a v = +1 v cm = 1v p-p c l = 16.3pf 10 isl28233, isl28433
10 fn6942.0 march 25, 2010 figure 24. psrr vs frequency, v s = 0.8v figure 25. cmrr vs temperature figure 26. psrr vs temperature figure 27. large signal step response (4v) figure 28. large signal step response (1v) figure 29. small signal step response (100mv) typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (hz) psrr (db) 100 1k 10k 100k 1m 10m v s = 0.8v r l = 100k a v = +1 v cm = 1v p-p c l = 16.3pf psrr- psrr+ 10 100 110 120 130 140 150 160 170 180 -40-20 0 20406080100 temperature (c) cmrr (db) n = 60 max median min v s = 2.5v v cm = 2.6v 100 110 120 130 140 150 160 170 180 190 -40 -20 0 20 40 60 80 100 n = 60 temperature (c) psrr (db) max median min v s = 2v to 5.5v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 time (s) signal (v) r l = 100k a v = 1 v out = 4v p-p c l = 3.7pf 0 0.2 0.4 0.6 0.8 1.0 1.2 0 102030405060708090100 time (s) signal (v) r l = 100k a v = 1 v out = 1v p-p c l = 3.7pf 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0 5 10 15 20 25 30 35 40 time (s) signal (v) r l = 100k a v = 1 v out = 100mv p-p c l = 3.7pf isl28233, isl28433
11 fn6942.0 march 25, 2010 figure 30. v oh vs temperature figure 31. v ol vs temperature figure 32. crosstalk vs frequency, v s = 0.8v figure 33. crosstalk vs frequency, v s = 2.5v figure 34. tci os histogram figure 35. tcib histogram typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) 4.976 4.978 4.980 4.982 4.984 4.986 4.988 -40-20 0 20406080100 n = 60 v s = 2.5v temperature (c) v oh (v) max min r l = 10k median 14 16 18 20 22 24 -40 -20 0 20 40 60 80 100 temperature (c) v ol (mv) max min n = 60 v s = 2.5v r l = 10k median -140 -130 -120 -110 -100 -90 -80 -70 -60 10 100 1k 10k 100k 1m frequency (hz) crosstalk (db) v s = 0.8v r l = open a v = 1 c l = 3.7pf v out = 1v p-p -140 -130 -120 -110 -100 -90 -80 -70 -60 10 100 1k 10k 100k 1m frequency (hz) crosstalk (db) v s = 2.5v r l = open a v = 1 c l = 3.7pf v out = 1v p-p 0 2 4 6 8 10 12 - 0 . 0 4 0 0 . 0 4 0 . 0 8 0 . 1 2 0 . 1 6 0 . 2 0 0 . 2 4 0 . 2 8 0 . 3 2 tci os (pa/c) frequency (units) 0 2 4 6 8 10 12 14 0 . 4 2 0 . 4 6 0 . 5 0 0 . 5 4 0 . 5 8 0 . 6 2 0 . 6 6 0 . 7 0 tci b (pa/c) frequency (units) isl28233, isl28433
12 fn6942.0 march 25, 2010 figure 36. tcv os histogram figure 37. i os vs v cm figure 38. i b+ vs v cm figure 39. i b- vs v cm figure 40. v os vs v cm typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open, t = +25c, unless otherwise specified. (continued) 0 2 4 6 8 10 12 14 16 -50 -42 -34 -26 -18 -10 -2 6 14 22 30 tcv os (nv/c) frequency (units) -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode voltage (v) input offset current (pa) max median min n = 10 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode voltage (v) i b+ bias current (pa) max median min n = 10 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i b- bias current (pa) n = 10 common mode voltage (v) max median min -10 -8 -6 -4 -2 0 2 4 6 8 10 input offset voltage (v) common mode voltage (v) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 n = 10 max median min isl28233, isl28433
13 fn6942.0 march 25, 2010 applications information functional description the isl28233 and isl28433 use a proprietary chopper-stabilized technique (see figure 41) that combines a 400khz main amplifier with a very high open loop gain (174db) chopper amplifier to achieve very low offset voltage and drift (2v, 0.02v/c typical) while consuming only 18a of supply current per channel. this multi-path amplifier architecture contains a time continuous main amplifier whose input dc offset is corrected by a parallel-connected, high gain chopper stabilized dc correction amplifier operating at 100khz. from dc to ~5khz, both amp lifiers are active with dc offset correction and most of the low frequency gain is provided by the chopper amplifier. a 5khz crossover filter cuts off the low frequency amplifier path leaving the main amplifier active out to the 400khz gain-bandwidth product of the device. the key benefits of this architecture for precision applications are very high open loop gain, very low dc offset, and low 1/f noise. the noise is virtually flat across the frequency range from a fe w millihertz out to 100khz, except for the narrow noise peak at the amplifier crossover frequency (5khz). rail-to-rail input and output (rrio) the rrio cmos amplifier uses parallel input pmos and nmos that enable the inpu ts to swing 100mv beyond either supply rail. the inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. this is effective in eliminating output distortion caused by high slew-rate input signals. the output stage uses common source connected pmos and nmos devices to achieve rail-to-rail output drive capability with 17ma current limit and the capability to swing to within 20mv of ei ther rail while driving a 10k load. in+ and in- protection all input terminals have internal esd protection diodes to both positive and negative supply rails, limiting the input voltage to within on e diode beyond the supply rails. for applications where either input is expected to exceed the rails by 0.5v, an external series resistor must be used to ensure the input currents never exceed 20ma (see figure 42). layout guidelines for high impedance inputs to achieve the maximum perf ormance of the high input impedance and low offset vo ltage of the isl28233 and isl28433 amplifiers, care should be taken in the circuit board layout. the pc board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. the use of guard rings around the amplifier inputs will further reduce leakage currents. figure 43 shows how the guard ring should be config ured. the guar d ring does not need to be a specific wi dth, but it should form a continuous loop around both inputs. by setting the guard ring voltage equal to the voltage at the non-inverting input, parasit ic capacitance is minimized as well. high gain, precision dc-coupled amplifier the circuit in figure 44 implements a single-stage dc-coupled amplifier with an input dc sensitivity of under 100nv that is only possible using a low vos figure 41. isl28233, isl28433 functional block diagram v out in- in+ 5khz crossover filter chopper stabilized dc offset correction main amplifier figure 42. input current limiting - + r in r l v in v out isl28433 in v+ figure 43. use of guard rings to reduce high impedance input guard ring pc trace + - isl28233, isl28433
14 fn6942.0 march 25, 2010 amplifier with high open loop gain. high gain dc amplifiers operating from low voltage supplies are not practical using typical low offset precision op amps. for example, the typical 100v v os and offset drift 0.5v/ c of a low offset op amp would produce a dc error of >1v with an additional 5mv/ c of temperature dependent error making it di fficult to resolve dc input voltage changes in the mv range. the 8v max v os and 0.06v/ c of the isl28233, isl28433 produces a temperature stable maximum dc output error of only 80mv with a maximum temperature drift of 0.06v/ c. the additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables dc voltages and voltage fluctuations well below 100nv to be easily detected with a simple single stage amplifier. isl28233, isl28433 spice model figure 45 shows the spice model schematic and figure 46 shows the net list for the isl28233, isl28433 spice model. the model is a simplified version of the actual device and simulates important parameters such as noise, slew rate, gain and phase. the model uses typical parameters from the ?electrical specifications table? on page 4. the poles and zeroes in the model were determined from the actual open and closed-loop gain and phase response. this enables the model to present an accurate ac representation of the actual device. the model is configured for ambient temperature of +25c. figures 47 through 54 show the characterization vs simulation results for the noise density, frequency response vs close loop gain, gain vs frequency vs cl and large signal step response (4v). license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licence to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including buy not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and the macro-model without prior notice. figure 44. high gain, precision dc-coupled amplifier - + 100 r l v in v out 1m 1m , 100 -2.5v +2.5v a cl = 10kv/v c f 0.018f isl28233, isl28433
15 fn6942.0 march 25, 2010 + - + - i1 i2 m1 m2 r2 r1 r3 r4 en r21 r22 dn1 v15 dn2 v16 cin1 cin2 vin+ vin- 7 13 12 4 7 13 12 4 + - + - + - + - 7 vv3 16 4 + - + - + - + - g2 g1 r6 r5 d1 v3 v4 d2 g4 g3 r8 r7 c1 c2 d3 v5 v6 d4 7 4 16 vv3 + - + - + - + - + - + - e1 g5 g5 r12 r11 l1 r10 r9 l2 g7 g8 r14 r13 c4 c3 g9 g10 d5 d6 d7 d8 g11 g10 r16 r15 v+ vout v- voltage noise input stage gain stage sr limit & first pole pole output stage zero/pole figure 45. spice circuit schematic isl28233, isl28433
16 fn6942.0 march 25, 2010 * isl28233, isl28433 macromodel * revision b, april 2009 * ac characteristics, voltage noise *copyright 2009 by intersil corporation *refer to data sheet ?license statement? use of *this model indicates y our acceptance with the *terms and provisions in the license statement. * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28233 3 2 7 4 6 * *voltage noise d_dn1 102 101 dn d_dn2 104 103 dn r_r21 0 101 120k r_r22 0 103 120k e_en 8 3 101 103 1 v_v15 102 0 0.1vdc v_v16 104 0 0.1vdc * *input stage c_cin1 8 0 0.4p c_cin2 2 0 2.0p r_r1 9 10 10 r_r2 10 11 10 r_r3 4 12 100 r_r4 4 13 100 m_m1 12 8 9 9 pmosisil + l=50u + w=50u m_m2 13 2 11 11 pmosisil + l=50u + w=50u i_i1 4 7 dc 92ua i_i2 7 10 dc 100ua * *gain stage g_g1 4 vv2 13 12 0.0002 g_g2 7 vv2 13 12 0.0002 r_r5 4 vv2 1.3meg r_r6 vv2 7 1.3meg d_d1 4 14 dx d_d2 15 7 dx v_v3 vv2 14 0.7vdc v_v4 15 vv2 0.7vdc * *sr limit first pole g_g3 4 vv3 vv2 16 1 g_g4 7 vv3 vv2 16 1 r_r7 4 vv3 1meg r_r8 vv3 7 1meg c_c1 vv3 7 12u c_c2 4 vv3 12u d_d3 4 17 dx d_d4 18 7 dx v_v5 vv3 17 0.7vdc v_v6 18 vv3 0.7vdc * *zero/pole e_e1 16 4 7 4 0.5 g_g5 4 vv4 vv3 16 0.000001 g_g6 7 vv4 vv3 16 0.000001 l_l1 20 7 0.3h r_r12 20 7 2.5meg r_r11 vv4 20 1meg l_l2 4 19 0.3h r_r9 4 19 2.5meg r_r10 19 vv4 1meg *pole g_g7 4 vv5 vv4 16 0.000001 g_g8 7 vv5 vv4 16 0.000001 c_c3 vv5 7 0.12p c_c4 4 vv5 0.12p r_r13 4 vv5 1meg r_r14 vv5 7 1meg * *output stage g_g9 21 4 6 vv5 0.0000125 g_g10 22 4 vv5 6 0.0000125 d_d5 4 21 dy d_d6 4 22 dy d_d7 7 21 dx d_d8 7 22 dx r_r15 4 6 8k r_r16 6 7 8k g_g11 6 4 vv5 4 -0.000125 g_g12 7 6 7 vv5 -0.000125 * .model pmosisil pmos (kp=16e-3 vto=10m) .model dn d(kf=6.4e-16 af=1) .model dx d(is=1e-18 rs=1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28233 figure 46. spice net list isl28233, isl28433
17 fn6942.0 march 25, 2010 v characterization vs simulation results figure 47. characterized input noise voltage density vs frequency figure 48. simulated input noise voltage density vs frequency figure 49. characterized frequency response vs closed loop gain figure 50. simulated frequency response vs closed loop gain figure 51. characterized gain vs frequency vs c l figure 52. simulated gain vs frequency vs c l frequency (hz) 10 100 1000 input noise voltage (nv/ hz 0.001 0.01 0.1 1 10 100 1k 10k 100k v+ = 5v av = 1 frequency (hz) 10 100 1000 input noise voltage (nv/ hz 0.1 1 10 100 1k 10k 100k v + = 5v a v = 1 -10 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) a v = 1 a v = 10 a v = 100 a v = 1000 v + = 5v v out = 10mv p-p c l = 3.7pf r l = 100k r g = 10k, r f = 100k r g = 100, r f = 100k r g = 1k, r f = 100k r g = open, r f = 0 10 100 1k 10k 100k 1m 10m frequency (hz) av = 1 av = 10 av = 100 av = 1000 rg = 1k, rf = 100k rg = 100, rf = 100k rg = 10m rf = 1 rg = 10k, rf = 100k -10 0 10 20 30 40 50 60 70 gain (db) frequency (hz) normalized gain (db) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 v+ = 5v r l = 100k av = +1 v out = 10mvp-p cl = 824pf c l = 224pf c l = 474pf c l = 51pf c l = 3.7pf c l = 104pf c l = 824pf c l = 474pf cl = 224pf c l = 824pf c l = 3.7pf frequency (hz) -10 -8 -6 -4 -2 0 2 4 6 8 10k 100k 1m 10m 1k 100 c l = 224pf normalized gain (db) isl28233, isl28433
18 fn6942.0 march 25, 2010 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl28233, isl28433 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php figure 53. characterized large signal step response (4v) figure 54. simulated large signal step response (4v) characterization vs simulation results (continued) time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 v+ = 5v rl = 100k av = 1 cl = 3.7pf v out = 4v p-p v out v in time (s) large signal (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 50 100 150 200 250 300 350 400 revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/25/10 fn6942.0 initial release. isl28233, isl28433
19 fn6942.0 march 25, 2010 isl28233, isl28433 package outline drawing m8.118a 8 lead mini small outlin e plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop 8l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to jedec mo-187-aa 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view side view 2 included. included. gauge plane 33 0.25 c a b b 0.10 c 0.08 c a b a 0.25 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 4.40 3.00 5.80 0.65 3.00.1 4.90.15 1.40 0.40 0.65 bsc pin# 1 id detail "x" 0.33 +0.07/ -0.08 0.10 0.05 3.00.1 1 2 8 0.860.09 seating plane and amse y14.5m-1994.
20 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6942.0 march 25, 2010 for additional products, see www.intersil.com/product_tree isl28233, isl28433 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
21 fn6942.0 march 25, 2010 isl28233, isl28433 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994

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